ENGtechnica

Tag: ChipDesign

  • Siemens Announces User2User 2025 N America Conference

    Siemens Announces User2User 2025 N America Conference

    Image: Siemens

    PLANO, TX, Feb 20, 2025 – Siemens EDA, a part of Siemens Digital Industries Software, has announced the Siemens EDA North America User2User (U2U) 2025 Conference, taking place on Tuesday, May 20, 2025, in Santa Clara, CA.

    User2User is a free-of-charge technical conference designed by engineers for engineers, offering an opportunity for industry professionals to collaborate, learn, and innovate. The event will feature technical sessions, keynote presentations, hands-on labs, and networking opportunities, all aimed at advancing electronic design automation (EDA) technology and methodology.

    Technology Tracks & Sessions

    Attendees will gain insights into the latest advancements and solutions from Siemens EDA, covering key topics such as:

    • 3DIC Chiplet Package Design
    • AI/ML
    • Aprisa Digital IC Implementation
    • Calibre Solutions Driving Customer Success
    • Cloud Adoption
    • Custom IC
    • Functional Design & Verification
    • Hardware-Assisted Verification
    • High-Level Synthesis/Power Analysis
    • Tessent Test Solutions

    Exclusive Post-Conference Technical Training – May 21, 2025

    For the second year in a row, Siemens EDA is offering an optional second day of technical training on Wednesday, May 21, 2025. This exclusive training will provide in-depth instruction on:

    • Introduction to Software Design Pattern Concepts in SystemVerilog & UVM
    • Tessent & IJTAG

    Attendees of these specialized training sessions will receive a free Online Digital Twin (ODT) license for the full self-paced training course, allowing them to deepen their expertise and apply hands-on labs in Siemens’ virtual cloud-enabled environment.

    Registration & Cost

    • User2User Conference (May 20): Free of charge, including sessions, lunch, and parking.
    • Optional Technical Training (May 21): $350

    For more details and registration, please visit Siemens EDA U2U website.

    Source: Siemens

    About Siemens Digital Industries Software

    Siemens Digital Industries Software provides comprehensive solutions for digital transformation, offering software and services that enable companies to improve product design, manufacturing, and operational processes. It serves a wide range of industries including automotive, aerospace, industrial machinery, electronics, and consumer products. Siemens Digital Industries Software has contributed towards innovation in manufacturing and product lifecycle management (PLM). The company is headquartered in Plano, TX, and is part of Siemens AG.

  • MediaTek, Cadence Partner to Accelerate 2nm Design Process

    MediaTek, Cadence Partner to Accelerate 2nm Design Process

    SAN JOSE, CA, Jan 23, 2025 – Cadence has announced that MediaTek has adopted the AI-driven Cadence Virtuoso Studio and Spectre X Simulator on the NVIDIA accelerated computing platform for its 2nm development. As design size and complexity continue to escalate, advanced-node technology development has become increasingly challenging for SoC providers. To meet the aggressive performance and turnaround time (TAT) requirements for its 2nm high-speed analog IP, MediaTek is leveraging Cadence’s proven custom/analog design solutions, enhanced by AI, to achieve a 30% productivity gain.

    “As MediaTek continues to push technology boundaries for 2nm development, we need a trusted design solution with strong AI-powered tools to achieve our goals,” said Ching San Wu, corporate vice president at MediaTek. “Closely collaborating with Cadence, we have adopted the Cadence Virtuoso Studio and Spectre X Simulator, which deliver the performance and accuracy necessary to achieve our tight design turnaround time requirements. Cadence’s comprehensive automation features enhance our throughput and efficiency, enabling our designers to be 30% more productive.”

    MediaTek has used the Virtuoso ADE Suite to add its AI-based optimization algorithm to streamline future product development. This has helped its designers work more efficiently on circuit designs. Cadence’s Spectre X running on NVIDIA H100 GPUs delivers the same accuracy as Spectre X running on CPUs while delivering up to a 6X performance improvement for post-layout simulations of large, advanced-node designs.

    “Improved performance and efficiency are key to advancing today’s complex chip design processes,” said Dion Harris, director of accelerated computing at NVIDIA. “With Cadence’s Spectre X running on NVIDIA Hopper GPUs, companies like MediaTek can accelerate the verification of their complex post-layout designs, maximize analog circuit simulation performance and reduce time to market.”

    MediaTek’s analog layout team now uses the Virtuoso Layout Suite device-level router for custom digital blocks in 2nm technology, improving layout efficiency.Additionally, MediaTek is leveraging AI and Virtuoso’s open platform to create a prototyping placement and low-power prediction process. This approach improves design productivity by 30%.

    “MediaTek’s validation of our latest Virtuoso Studio release and Spectre X Simulator on NVIDIA’s accelerated computing platform demonstrates that Cadence’s continued investment in enhancing our industry-leading custom design solutions and AI tools is a game changer for our customers’ most challenging 2nm designs,” said Vinod Kariat, corporate vice president and general manager of the Custom Products Group at Cadence. “Bringing the power of AI and GPUs to Spectre X enables MediaTek to solve its large-scale verification simulation challenges even more quickly, without sacrificing accuracy.”

    Source: Cadence